/*
 * Copyright (C) 2015 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-06-09 10:08:26
 *
 */


#ifndef ANLG_PHY_TOP_H
#define ANLG_PHY_TOP_H

#define CTL_BASE_ANLG_PHY_TOP 0x403E0000


#define REG_ANLG_PHY_TOP_ANALOG_TOP_REG_SEL_CFG_0      ( CTL_BASE_ANLG_PHY_TOP + 0x0000 )
#define REG_ANLG_PHY_TOP_ANALOG_TOP_REG_SEL_CFG_1      ( CTL_BASE_ANLG_PHY_TOP + 0x0004 )
#define REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_0         ( CTL_BASE_ANLG_PHY_TOP + 0x0008 )
#define REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_1         ( CTL_BASE_ANLG_PHY_TOP + 0x000C )
#define REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_2         ( CTL_BASE_ANLG_PHY_TOP + 0x0010 )
#define REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_DUMY      ( CTL_BASE_ANLG_PHY_TOP + 0x0014 )

/* REG_ANLG_PHY_TOP_ANALOG_TOP_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_EFUSE_1_1_EFS1_ENK2           BIT(23)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_EFUSE_1_1_EFS1_ENK1           BIT(22)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_EFUSE_1_0_EFS1_ENK2           BIT(21)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_EFUSE_1_0_EFS1_ENK1           BIT(20)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_LPLL_REF_SEL          BIT(19)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_REF_SEL         BIT(18)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_PD              BIT(17)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_LPLL_PD               BIT(16)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_GPLL_PD               BIT(15)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_IPLL_PD               BIT(14)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_RST             BIT(13)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_LPLL_RST              BIT(12)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_GPLL_RST              BIT(11)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_IPLL_RST              BIT(10)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV2_EN         BIT(9)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV3_EN         BIT(8)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV5_EN         BIT(7)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV7_EN         BIT(6)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV2_EN          BIT(5)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV3_EN          BIT(4)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV5_EN          BIT(3)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_GPLL_CLKOUT_EN        BIT(2)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_IPLL_DIV2_EN          BIT(1)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_PLL_TOP_IPLL_DIV3_EN          BIT(0)

/* REG_ANLG_PHY_TOP_ANALOG_TOP_REG_SEL_CFG_1 */

#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_USB20_USB20_PS_PD_S           BIT(20)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_USB20_USB20_PS_PD_L           BIT(19)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_S    BIT(18)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_L    BIT(17)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_S    BIT(16)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_L    BIT(15)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_S  BIT(14)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_L  BIT(13)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_DPLL_DIV_SEL     BIT(12)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_DPLL_CLKOUT_EN   BIT(11)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_DPLL_PD          BIT(10)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_DPLL_RST         BIT(9)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_THM_PD           BIT(8)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_THM_RSTN         BIT(7)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_DPLL_THM_TOP_THM_RUN          BIT(6)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL_CLKOUT_EN   BIT(5)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL_PD          BIT(4)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MPLL_THM_TOP_MPLL_RST         BIT(3)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_PD           BIT(2)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_RSTN         BIT(1)
#define BIT_ANLG_PHY_TOP_DBG_SEL_ANALOG_MPLL_THM_TOP_THM_RUN          BIT(0)

/* REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_0 */

#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_REF_SEL(x)               (((x) & 0x3) << 25)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_REF_SEL(x)              (((x) & 0x3) << 23)
#define BIT_ANLG_PHY_TOP_ANALOG_BB_TOP_DOUT_TSEN_SDADC_SEL            BIT(22)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_IPLL_LOCK_DONE                BIT(21)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_IPLL_DIV3_EN                  BIT(20)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_IPLL_DIV2_EN                  BIT(19)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_IPLL_RST                      BIT(18)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_IPLL_PD                       BIT(17)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_GPLL_LOCK_DONE                BIT(16)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_GPLL_CLKOUT_EN                BIT(15)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_GPLL_RST                      BIT(14)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_GPLL_PD                       BIT(13)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_LOCK_DONE                BIT(12)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_DIV5_EN                  BIT(11)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_DIV3_EN                  BIT(10)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_DIV2_EN                  BIT(9)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_RST                      BIT(8)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_LPLL_PD                       BIT(7)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_LOCK_DONE               BIT(6)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_DIV7_EN                 BIT(5)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_DIV5_EN                 BIT(4)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_DIV3_EN                 BIT(3)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_DIV2_EN                 BIT(2)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_RST                     BIT(1)
#define BIT_ANLG_PHY_TOP_ANALOG_PLL_TOP_TWPLL_PD                      BIT(0)

/* REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_1 */

#define BIT_ANLG_PHY_TOP_ANALOG_USB20_USB20_PS_PD_S                   BIT(25)
#define BIT_ANLG_PHY_TOP_ANALOG_USB20_USB20_PS_PD_L                   BIT(24)
#define BIT_ANLG_PHY_TOP_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_S            BIT(23)
#define BIT_ANLG_PHY_TOP_ANALOG_MIPI_DSI_4LANE_DSI_PS_PD_L            BIT(22)
#define BIT_ANLG_PHY_TOP_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_S            BIT(21)
#define BIT_ANLG_PHY_TOP_ANALOG_MIPI_CSI_4LANE_CSI_PS_PD_L            BIT(20)
#define BIT_ANLG_PHY_TOP_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_S          BIT(19)
#define BIT_ANLG_PHY_TOP_ANALOG_MIPI_CSI_2P2LANE_CSI_PS_PD_L          BIT(18)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_DPLL_DIV_SEL(x)          (((x) & 0xF) << 14)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_THM_RUN                  BIT(13)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_THM_RSTN                 BIT(12)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_THM_PD                   BIT(11)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_DPLL_LOCK_DONE           BIT(10)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_DPLL_CLKOUT_EN           BIT(9)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_DPLL_RST                 BIT(8)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_DPLL_PD                  BIT(7)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_THM_RUN                  BIT(6)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_THM_RSTN                 BIT(5)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_THM_PD                   BIT(4)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_MPLL_LOCK_DONE           BIT(3)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_MPLL_CLKOUT_EN           BIT(2)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_MPLL_RST                 BIT(1)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_MPLL_PD                  BIT(0)

/* REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_2 */

#define BIT_ANLG_PHY_TOP_ANALOG_TSENADC_CLK_SEL                       BIT(27)
#define BIT_ANLG_PHY_TOP_ANALOG_OSCADC_CLK_SEL                        BIT(26)
#define BIT_ANLG_PHY_TOP_ANALOG_EFUSE_1_1_EFS1_ENK2                   BIT(25)
#define BIT_ANLG_PHY_TOP_ANALOG_EFUSE_1_1_EFS1_ENK1                   BIT(24)
#define BIT_ANLG_PHY_TOP_ANALOG_EFUSE_1_0_EFS1_ENK2                   BIT(23)
#define BIT_ANLG_PHY_TOP_ANALOG_EFUSE_1_0_EFS1_ENK1                   BIT(22)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_THM_DATA(x)              (((x) & 0xFF) << 14)
#define BIT_ANLG_PHY_TOP_ANALOG_DPLL_THM_TOP_THM_VALID                BIT(13)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_THM_DATA(x)              (((x) & 0xFF) << 5)
#define BIT_ANLG_PHY_TOP_ANALOG_MPLL_THM_TOP_THM_VALID                BIT(4)
#define BIT_ANLG_PHY_TOP_DSI_4LANE_ISO_SW_EN                          BIT(3)
#define BIT_ANLG_PHY_TOP_CSI_4LANE_ISO_SW_EN                          BIT(2)
#define BIT_ANLG_PHY_TOP_CSI_2P2LANE_ISO_SW_EN                        BIT(1)
#define BIT_ANLG_PHY_TOP_USB20_ISO_SW_EN                              BIT(0)

/* REG_ANLG_PHY_TOP_ANALOG_TOP_REG_CTRL_DUMY */

#define BIT_ANLG_PHY_TOP_ANALOG_TOP_DUMY_IN(x)                        (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_TOP_ANALOG_TOP_DUMY_OUT(x)                       (((x) & 0xFFFF))


#endif /* ANLG_PHY_TOP_H */

